Kernel Formation in Garpcc

The Garp project [3] quantitatively investigates the benefits of adding an on-chip dynamically reconfigurable coprocessor to a standard instruction processor. Intended for acceleration of loops, Garp’s coprocessor performs iteration control and both streaming and random memory accesses without assistance from the instruction processor. The companion project Garpcc [2] investigates whether new compilation approaches can enable automatic exploitation of the coprocessor starting from standard C code. No hints regarding hardware/software partitioning are expected, although profiling data is assumed. A key technique used by Garpcc is to exclude rarelytaken control paths from the coprocessor implementation of the loop [1]; when an iteration takes an excluded path, control hops back to the instruction processor to execute the remainder of that iteration, and control returns to the coprocessor at the start of the next iteration. The set of included paths is called the kernel of the loop. This approach of excluding some paths but including others closely parallels hyperblock formation in VLIW compilation as described by Mahlke et.al. [5], especially since predicated execution is used to expose parallelism across the included paths. Garpcc builds a dataflow graph (DFG) using an aggressively speculative form of predication where safe operations along all included paths are performed unconditionally, and at control flow merge points, multiplexors controlled by predicates select the appropriate values for further use. Only non-safe operations (stores and exits) are directly guarded by predicates. The synthesis step from DFG to hardware utilizes a fully spatial approach (no sharing of function units / modules). Despite similarities with VLIW hyperblock formation, Garpcc’s framework and decision process for choosing included paths differs significantly from that described by Mahlke.